@misc{oai:ir.soken.ac.jp:00002172,
 author = {Galle Mannakarage, Mannakkara  Chammika and ガレイ　マナカラジ, マナカラ　チャミカ and GALLE MANNAKARAGE, Mannakkara Chammika},
 month = {2016-02-17, 2016-02-17},
 note = {Over the past couple of decades, the digital design technology scales to date remarkably satisfying the Moore's Law. The circuits became denser with the scaling of transistor and interconnect, and operating frequencies increased several orders of magnitudes during this period. This poses challenges to digital circuit design in a variety of areas including clock distribution, power management, process migration, fault-tolerance, etc. A lot of research effort goes to tackle these issues under the synchronous design methodology which currently dominates the digital design world. However, the magnitude of the challenges poised has also revitalized the asynchronous design methodology explored in this work, as it inherently address some of key issues.

The main philosophy of the asynchronous design practices is to compose a digital circuit as a collection of autonomous parts communicating with each other locally, as opposed to synchronous design which controls the circuit with a centralized clock signal. Without a global clock or clock domains the designs eliminate the ever increasing problems of high power and area consumption, skew minimization, etc. associated with the clocks. Each component operates only when required in an inherently power efficient manner generating a low electromagnetic(EM) noise. The control and data flow is inherently elastic providing immunity to transistor-to-transistor variability in the manufacturing process, thus providing better technology migration characteristics. These are only a few of the main advantages of asynchronous design.

The spectrum of design styles under asynchronous paradigm varies from bundled data communication model which can employ synchronous-like data processing elements with careful delay matching for completion detection, to delay-insensitive model which can accommodate arbitrary delays in the design. The focus of the is work is on the for mer style -the bundled data model- which is more close to synchronous design practices. Synchronous circuits, specially pipelined circuits can be transformed to these form asynchronous designs with relative ease. In a time when digital design primarily done in synchronous manner, the work presented here will be significant in harnessing the strengths of asynchronous practices by migrating from synchronous to asynchronous with low effort.

This PhD dissertation presents is a new pipeline controller based on Early Acknowledgement protocol for bundled data asynchronous circuits. The Early Acknowledgement protocol is a hybrid of 2-phase and 4-phase hand-shake protocols, two widely used protocols for bundled data communication. The new Early Acknowledgement protocol combines the advantages of 2-phase and 4-phase protocols and the controller that is presented exploits them. It mainly employs the return-to-zero control signals like 4-phase protocol retaining the simplicity for interfacing and composition of non-linear controllers. At the same time, the controller overhead can be hidden in the Early Acknowledgement protocol which gives the performance comparable to that of 2-phase protocol. First a linear controller for the Early Acknowledgement protocol is proposed which can be deployed in straight pipelines. In order to further the claims of the proposed controller, a non-linear controller for Early Acknowledgement protocol to perform conditional branch operation is also proposed using the above mentioned linear controller. Though simple in con-struction, it has been observed to be superior in performance compared to its 2-phase and 4-phase counter parts.

The performances of the both linear and non-linear controllers are evaluated analytically. Constraints for the proper operation of the controllers are obtained and the conditions for the optimal operation i.e. when the controller hides aII its overhead and operate efficiently are derived. The performances of the controllers are obtained when the controllers are operating in two different modes: pipelines with logic processing and pipelines without logic processing. Similar performance analysis for the controllers of 2-phase and 4-phase protocols (both linear and non-linear controllers) is carried out. The findings outline the design choices available, cost vs. performance benefits and design constraints to be satisfied in employing 2-phase, 4-phase and Early Acknowledgement controller in bundled data communication design.

A case study which carried out to analyse the performance of the each controller in a practical application environment is presented at the end. The target was to build an accelerator module to solve set of linear equations using Gauss-Seidel method which can be used in a core of a Finite Element Method (FEM) analysis system. Three accelerator modules are designed using 2-phase, 4-phase and Early Acknowledgement protocols for the control path. All the designs are implemented on a Xilinx Virtex-4 FPGA platform.
Performance of these modules which essentially compares the protocol is analysed and presented. The conclusions highlight the advantages and best use case scenarios of the proposed controllers.

In conclusion, this work as highlighted the importance of little known EA protocol by proposing a controller for it to harness its advantages. This work serves the main source of any analytical and practical comparison of these protocols. The results of the work will strengthen the importance of EA protocol and encourage the use of it in applications where it exhibit to work efficiently., application/pdf, 総研大甲第1386号},
 title = {Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol},
 year = {}
}